1. Field of the Invention
The present invention relates to a data driver for outputting an analog grayscale voltage to each data bus line and a display utilizing the same.
2. Description of the Related Art
An example of a configuration of a liquid crystal display panel having conventional data drivers loaded thereon will be described with reference to FIG. 6. FIG. 6 shows a schematic configuration of a conventional liquid crystal display panel 101 having thin film transistors (TFTs) whose channel layers are formed from, for example, amorphous silicon (a-Si) as switching elements. A plurality of data bus lines Ld extending in the vertical direction of the figure are formed in a display area 90 of the panel 101 in parallel in the lateral direction of the figure, and a plurality of gate signal lines (not shown) extending in a direction substantially perpendicular to the data bus lines Ld are formed in parallel in the vertical direction of the figure. Each of the data bus lines Ld is connected to any of data drivers 103 through 117 to be driven thereby. Each of the plurality of gate signal lines is driven by a gate driver which is omitted in the figure.
For example, in the case of a color display which is a panel for displaying a matrix consisting of 800 horizontal pixels and 600 vertical pixels, i.e., an SVGA (super video graphics array) and in which one pixel is formed by three subpixels, i.e., red (R), green (G) and blue (B) pixels, the number of subpixels displayed on one gate signal line (scan line) is 2400 (800×3). In order to drive the liquid crystal display 101 using a line sequential driving method, for example, four of the eight data drivers 103 through 117 each of which is capable of driving 300 data bus lines Ld are mounted at each of the upper and lower ends of the data bus lines Ld. The data bus lines Ld are sequentially alternately connected to the data drivers 103 through 117 provided at the upper and lower parts of the panel, for example, in the left-to-right direction of the figure.
Let us assume that the data bus lines Ld are numbered starting with the leftmost line in the figure. Then, the data driver 103 drives data bus lines Ld with odd numbers from 1 to 599, and the data driver 111 drives data bus lines Ld with even numbers from 2 and 600. Similarly, the data drivers 105, 107 and 109 drive data bus lines Ld with odd-numbers from 601 to 1199, from 1201 to 1799 and from 1801 to 2399 respectively, and the data drivers 113, 115 and 117 drive data bus lines Ld with even numbers from 602 to 1200, from 1202 to 1800 and from 1802 to 2400 respectively.
Display data for one scan line are normally output from a system such as a computer connected to the liquid crystal display 101 in the (ascending or descending) order of the numbers of the data bus lines Ld. Therefore, there is separately provided an allocation circuit 119 for allocating each item of the display data to any of the data drivers 103 through 117 such that each item of the display data is output from a predetermined data bus line Ld. Display data in three colors R, G and B for each pixel transmitted from the system are input to the data drivers 103 through 117 as digital data having a number of bits corresponding to the number of grayscales to be displayed whether the data are analog data or digital data.
The data drivers 103 through 117 shown in FIG. 6 have the same configuration, and a schematic structure of the same will be described using FIG. 7 with reference to the data driver 103 as an example. The data driver 103 has a shift register 500 to which digital grayscale data Data are input. For example, the grayscale data Data are red (R) data Rd (0-5), green (G) data Gd (0-5) and blue (B) data Bd (0-5) each of which consists of six bits, which allows 64 grayscales to be displayed for each of the colors.
For example, the shift register 500 comprises 300 stages to allow grayscale data to be output to 300 data bus lines by one data driver 103. The shift register 500 sequentially fetches the grayscale data Data into the stages in synchronism with dot clocks DCLK transmitted from a control portion which is not shown.
An output terminal of each of the first through 300th stages of the shift register 500 is connected to a latch circuit 502 provided downstream thereof. When a latch pulse LP is output with the grayscale data Data stored in all stages of the shift register 500, the latch circuit 502 latches the grayscale data in each stage of the shift register 500.
A reference voltage selection circuit is provided downstream of the latch circuit 502. The reference voltage selection circuit has one ladder resistor portion 506 for supplying 64 voltage levels to the data bus lines and a selector portion 508 provided for each data bus line.
The ladder resistor portion 506 is provided by connecting 63 resistors R1 through R63 in series. A voltage V0 is applied to one terminal of the resistor R1, and a voltage V63 is applied to one terminal of the resistor R63. A grayscale voltage line l1 for supplying the voltage V0 to the selector portions 508 is extended from the ladder resistor portion 506. A grayscale voltage line l64 for supplying the voltage V63 to the selector portions 508 is also extended. Grayscale voltage lines l2 through l62 are extended from connecting points between the adjoining resistors by connecting taps thereto, and 64 voltage levels from the voltage V0 up to the voltage V63 are supplied to the selector portions 508 through the grayscale voltage lines l1 through l64 as a result of resistance division.
The selector portions 508 will now be described. For example, the selector portion 508 for the first data bus line has 64 decoders S1-1 through S64-1. Each of the decoders S1-1 through S64-1 has six switching elements Tr1 through Tr6 which are constituted by, for example, p-channel type MOSFETs. The drain electrodes of the first switching elements Tr1 provided at the decoders S1-1 through S64-1 are sequentially connected to the 64 grayscale voltage lines l1 through l64 extended from the ladder resistor portion 506.
The source electrodes of the switching elements Tr1 are connected to the drain electrodes of the switching elements Tr2 at the subsequent stages. Similarly, the switching elements Tr1 through Tr6 are connected in series in the order listed, and the source electrode of the switching element Tr6 is connected to a first output line Out1. The output line Out1 is connected to a first data bus line through a buffer 504.
The gate electrode of the switching element Tr1 is connected to either bit lines D1 or /D1 for the first bit of grayscale data consisting of six bits held for the first data bus line in the latch circuit 502. The symbol “/” indicates that the bit line is activated by a signal at a low (L) level. Similarly, the gate electrodes of the switching elements Tr2 through Tr6 of the decoders S1-1 through S64-1 are sequentially connected to bit lines D2 (or /D2) through D6 (or /D6) of the second through sixth bits of the grayscale data consisting of six bits held for the first data bus line in the latch circuit 502.
Although not described in detail, the bit lines D or /D connected to the gate electrodes of the switching elements Tr1 through Tr6 of the decoders S1-1 through S64-1 may be appropriately selected and connected to select one of the voltages at 64 levels in accordance with the grayscale data held in the latch circuit 502. On the first data bus line, for example, all of the switching elements Tr1 through Tr6 of any one of the decoders S1-1 through S64-1 may be turned on in accordance with the grayscale data held in the latch circuit 502, and at least one of the switching elements Tr1 through Tr6 of the other decoders may be turned off.
As a result, a desired analog grayscale voltage can be output to the first data bus line from the grayscale voltage line l connected to the decoder whose switching elements Tr1 through Tr6 have been all turned on. A desired analog grayscale voltage can be selected and output to the m-th data bus line through completely the same operation.
The analog grayscale voltage output to the output line Out1 is applied to the drain electrode of a pixel TFT (not shown) connected to the first data bus line through a buffer 504. The grayscale voltages are applied from pixel TFTs which have been turned on by gate pulse transmitted to a predetermined gate bus line to the pixel electrodes respectively, thereby performing grayscale display for one gate bus line.
In order to prevent deterioration of the liquid crystal, a grayscale voltage applied to the liquid crystal is normally subjected to the so-called inversion (alternate) driving in which the polarity of the voltage is inverted for each frame. Therefore, the data drivers have a configuration including a ladder resistor and decoders such that 64 levels each can be output with a positive polarity (+V) and negative polarity (−V) relative to a common potential. For simplicity of description, FIG. 7 shows only the configuration of the positive polarity side.
The data driver is subjected to performance evaluation and functional tests at the final stage of the manufacturing steps. Such evaluation and tests are conducted to detect any defect of the data driver by operating it under conditions which are the same as actual operating conditions. Specifically, 64 kinds of grayscale data are sequentially output to all of the selectors 508, and analog grayscale voltages output by the output lines Out1 through Outm are monitored with a tester. If the level of the output signal from any of the output lines Out1 through Outm falls below a reference level, the data driver is determined as defective.
For example, let us assume that V0=0 V and V63=5 V at the positive polarity side and that V0=0 V and V63=−5 V at the negative polarity side. Then, when there are 64 levels for each polarity as described above, the voltage difference between grayscales is only about 80 mV. Further, when 128 or 256 grayscales are to be achieved, the voltage difference between the grayscales is further reduced to a value in the same from about 20 mV to 40 mV.
Therefore, when the performance evaluation and functional tests of the data drivers are attempted by applying grayscale data sequentially, the small grayscale voltage difference between adjoining grayscales as described above results in a need for testers having excellent display resolving power and relatively high accuracy. This results in a problem in that the cost required for the tests is increased.
Further, the output of the output lines Out1 through Outm must be monitored after the levels of the analog grayscale voltages become sufficiently stable. This has resulted in a problem in that the grayscale data can not be switched at a high speed to conduct the tests in a short time. Furthermore, since the above-described operation must be repeated for a multiplicity of decoders S, a problem arises in that the testing takes a long time.
There is another problem in that a test can not be conducted in which a stress voltage is applied between wirings to reject data drivers having foreign substances that have been deposited between adjoining grayscale voltage lines at manufacturing steps but have not caused any short-circuit as defective products. Thus, a problem can arise in that data drivers which can become defective as time passes are mounted on a liquid crystal panel to cause display defects of the liquid crystal display after the shipment of the product.